In high speed serial data communication systems, Inter Symbol interference (ISI) is a form of distortion of a signal in which one symbol interferes with subsequent symbols. This is an unwanted phenomenon because the inter symbol interference generates an effect similar to noise, thereby increasing the Bit Error Rate of the system.
A signal sent from a gigabit per second transmitter on the I/O pin of one chip travels first along a trace on a plug-in card, through cables and then across a backplane to another plug-in card that contains the receiving chip. The signal often becomes degraded by random and periodic jitter, duty cycle distortion, inter symbol interference, frequency-selective attenuation, crosstalk, and the like. The ISI impairment is caused by reflections, typically caused in turn by impedance mismatch at various interconnection discontinuities.
Today, data rates are usually well above 1 Gb/s, so an echo decay time is longer than the pulse spacing, and the received pulse is mixed up with echoes of the previous pulse. There is a need to mitigate these impairments. Design of adequate mitigating algorithms, such as a pre-emphasis filter for the transmitter and a decision feedback equalizer (DFE) for the receiver, requires an accurate model of the impairment.
The impairments are modeled with the help of S-Parameter Touchstone files of the cables, interconnects and backplane to measure the BER tolerance of their receivers. This test is called receiver margin testing.
Signal integrity engineers carry out jitter tolerance/margin testing on digital receivers of high speed serial standards, such as HDMI, Display Port, SATA, PCI-E and the like. The jitter tolerance/receiver margin testing requires signals to be generated with various amounts of random and periodic jitter, duty cycle distortion and inter symbol interference. Some high speed serial standards recommend hardware cable emulators for emulating ISI effects. In the case of the HDMI (High Definition Multimedia Interface) standard, the recommended hardware cable emulators are produced by Agilent Technologies, Santa Clara, Calif., which produce fixed amounts of ISI. These cable emulators have a typical copper attenuation. The operational bandwidths of these cable emulators are restricted due to hardware constraints. For different pixel clock rates of HDMI, different hardware emulators are used for jitter tolerance tests. This process of using hardware cable emulators restricts the test conditions required for testing receiver performance. The amount of ISI on a signal at a particular data rate is limited.
FIG. 1 shows a representative test setup 10 for HDMI compliance testing of a device under test (DUT) 12. An arbitrary waveform generator 14, such as an AWG710, manufactured and sold by Tektronix, Inc., Beaverton, Oreg., generates and outputs differential clock signals, CL and CL, that are coupled to bias-tees 16. The bias-tees 16 are required to bring the differential clock signals, CL and CL, to the required TMDS (Transitioned-Minimized Differential Signaling) levels. The output differential clock signals, CL and CL, from the bias-tees 16 are coupled to an adapter board 18, such as a ET-HDMIC-TPA-R Receptacle Board, manufactured and sold by Efficere Technologies, Washougal, Wash., via Transition Time Converter (TTC) modules 20. The TTC modules 20 slow the rise time of the differential clock signals, CL and CL, to be in compliance with the HDMI compliance testing standard. In the test setup of FIG. 1, the bias-tees 18 are powered by a DC output from a data timing generator 22, such as a Data Timing Generator DTG5334, manufactured and sold by Tektronix, Inc., Beaverton Oreg. The arbitrary waveform generator 14 has two digital marker outputs, M1 and M2, which are used for synchronization, with the M1 marker connected to an external clock input of the data timing generator 22 and the M2 marker coupled to a serial trigger input of the data timing generator 22. The data timing generator 22 generates differential data signals, D0, D0, D1, D1, D2, D2, that are coupled to the adapter board 18 via TTC modules 20. As with the differential clock signal, the TTC modules 20 slow the rise time of the differential data signals D0, D0, D1, D1, D2, D2 to be in compliance with the HDMI compliance testing standard. A DC power supply 24 couples +5V DC and ground to the adapter board 18. The differential clock and data signals are coupled to the DUT 12 via a cable emulator 26. The cable emulator 26, such as the E4887A-101 and E4887A-102 Cable Emulators sold by Agilent Technologies, Santa Clara, Calif., emulates the characteristics of worst-case but compliant cable. The signals applied to the DUT 12 can be monitored using a measurement test instrument 28, such as a digital oscilloscope, to verify compliance with a particular HTMI standard.